[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

This revision was automatically updated to reflect the committed changes. Closed by commit rG2db700215a2e: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic (authored by kerbowa). Herald added a subscriber: kosarev. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

rampitec accepted this revision. rampitec added a comment. LGTM Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124700/new/ https://reviews.llvm.org/D124700 ___ cfe-commits mailing list [email protected]

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

kerbowa updated this revision to Diff 427747. kerbowa added a comment. Herald added a subscriber: jsilvanus. Use i32. Output hex. Fix hazard rec tests for pseudo instructions. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124700/new/ https://review

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

arsenm added a comment. Can you add a test to make sure the hazard recognizer and code size estimate don’t think this is a real instruction Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124700/new/ https://reviews.llvm.org/D124700 ___

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

rampitec accepted this revision. rampitec added a comment. This revision is now accepted and ready to land. In D124700#3483715 , @kerbowa wrote: > In D124700#3483633 , @rampitec > wrote: > >> In D124700#3483609 <

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

kerbowa added a comment. In D124700#3483633 , @rampitec wrote: > In D124700#3483609 , @kerbowa wrote: > >> In D124700#3483556 , @rampitec >> wrote: >> >>> You do not hand

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

rampitec added a comment. In D124700#3483609 , @kerbowa wrote: > In D124700#3483556 , @rampitec > wrote: > >> You do not handle masks other than 0 yet? > > We handle 0 and 1 only. Do you mean 1 is supported simp

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

kerbowa added a comment. In D124700#3483556 , @rampitec wrote: > You do not handle masks other than 0 yet? We handle 0 and 1 only. Comment at: llvm/include/llvm/IR/IntrinsicsAMDGPU.td:219 +// MASK = 0: No instructions may be sched

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

rampitec added a comment. You do not handle masks other than 0 yet? Comment at: llvm/include/llvm/IR/IntrinsicsAMDGPU.td:219 +// MASK = 0: No instructions may be scheduled across SCHED_BARRIER. +// MASK = 1: Non-memory, non-side-effect producing instructions may be +//

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

kerbowa updated this revision to Diff 426169. kerbowa added a comment. Add mir tests. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D124700/new/ https://reviews.llvm.org/D124700 Files: clang/include/clang/Basic/BuiltinsAMDGPU.def clang/test/Cod

[PATCH] D124700: [AMDGPU] Add llvm.amdgcn.sched.barrier intrinsic

kerbowa created this revision. Herald added subscribers: hsmhsm, foad, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, jvesely, kzhuravl, arsenm. Herald added a project: All. kerbowa requested review of this revision. Herald added subscribers: llvm-commits, cfe-commits, wdng. Herald added proj